Regviz

Freescale Semiconductor /MKS22F12 /CAN1 /IFLAG1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IFLAG1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MKS22F12/CAN1/IFLAG1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)BUF0I 0 (0)BUF4TO1I 0 (0)BUF5I 0 (0)BUF6I 0 (0)BUF7I 0 (0)BUF31TO8I

BUF7I=0, BUF0I=0, BUF31TO8I=0, BUF6I=0, BUF4TO1I=0, BUF5I=0

Description

Interrupt Flags 1 register

Fields

BUF0I

Buffer MB0 Interrupt Or Clear FIFO bit

0 (0): The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.

1 (1): The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
BUF4TO1I

Buffer MB i Interrupt Or “reserved”

0 (0): The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.

1 (1): The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
BUF5I

Buffer MB5 Interrupt Or “Frames available in Rx FIFO”

0 (0): No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1

1 (1): MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
BUF6I

Buffer MB6 Interrupt Or “Rx FIFO Warning”

0 (0): No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1

1 (1): MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
BUF7I

Buffer MB7 Interrupt Or “Rx FIFO Overflow”

0 (0): No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1

1 (1): MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
BUF31TO8I

Buffer MBi Interrupt

0 (0): The corresponding buffer has no occurrence of successfully completed transmission or reception.

1 (1): The corresponding buffer has successfully completed transmission or reception.

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data